The present invention generally relates to a memory control unit for use in a memory system of the type incorporating a plurality of memory banks. The present invention more particularly relates to such a memory control unit for use in a memory system including a plurality of dynamic random access memory (DRAM) banks and which includes a memory bank comparator which generates control signals responsive to an intermediate memory address to indicate, on a cycle-by-cycle basis, if the memory address is a valid address, which memory bank is being addressed, whether memory bank interleaving is possible, and what type of memory access cycle is required. The memory control unit, responsive to the memory bank comparator control signals and the intermediate memory address generates a row and column memory address, row and column address strobe signals and write-enable signals in properly timed relation to access the memory location in the proper memory bank.
The present invention is further directed to a memory unit for use with the memory control unit and which provides balanced row and column address strobe signal loads to preclude row and column address strobe signal timing skew.
Memory systems are well known in the art. Such systems are used in many applications including persona. computers. Memory systems provide program and operating data to associated central processing units to enable the central processing units to execute program instructions. In applications where a large amount of memory space is required, such as in personal computer applications, memory systems may include more than one memory bank. The memory banks may be formed with dynamic random access memories which are extremely popular in such applications because of their extremely high memory density. Each bank is divided into pages of, for example, 16KB pages. In this case, for example, a 256KB DRAM bank will include sixteen pages.
In order to access such memories, central processing units provide a multiple-bit address including a first portion containing an index into a 16KB memory page and a second portion which includes memory page pointers. In order to provide proper and organized memory utilization, the central processing unit memory address second portion pointers are translated by an address manager translation unit in accordance with stored translation parameters to provide an intermediate or translated address including the central processing unit memory address first portion which is not translated and a translated second portion which includes an address of the proper page to be accessed.
The translated address is then conveyed to a memory control unit which acts upon the translated address to derive a memory row and column address within the addressed page and row and column address strobe signals to be applied to the memory bank which includes the addressed page. In this manner, the available memory space is efficiently utilized and organized.
In a typical system, when a byte of data is to be stored, each memory bank is provided with the same memory address by the memory control unit. The particular memory location is selected with the application of the row address along with a row address strobe signal to the proper memory bank and then the column address along with a column strobe signal to the proper memory bank. A write-enable signal is then applied to each memory bank by the memory control unit which is maintained as the byte of data is conveyed from the memory control unit to each bank. Because only one bank is enabled by the strobe signals to receive the row and column address, the byte or word of data is stored within its own unique storage location.
Enhancements have been added to this general memory accessing procedure to improve upon memory access time. For example, a paging mode has been adopted wherein, instead of providing a newly generated row strobe signal during each cycle, the row strobe signal is maintained while new column addresses and column strobe signals are generated. The row strobe signal is maintained until a new row address is detected. This reduces addressing time and has been found to be advantageous since data is normally stored in multiple bytes with a given memory bank being accessed for a number of consecutive cycles.
Another enhancement has been the interleave mode. Interleaving is the practice of storing consecutive bytes of data in alternating or successive memory banks. This practice speeds up memory access because it counters the effect of row address strobe precharge. Hence, while a byte of data is stored in a memory bank, the row address strobe for the previous memory bank may be precharged fully and be ready for the next byte of data to be entered into that memory bank.
In addition to the foregoing, dynamic random access memories have been improved so that such devices are available in different types with each type corresponding to a respective different storage capacity. There are basically three different dynamic random access memory types, a 256KB type, a 1MB type, and a 4MB type. These different memory types afford flexibility to the ultimate user who may wish to tailor the storage size to a particular application or to increase the storage size of an existing system. Unfortunately, each memory type requires a different type of access cycle. This is mainly due to the need for a different number of address bits for each type. For example, the 256KB type requires nine row and nine column address bits, the 1MB type requires ten row and ten column address bits, and the 4MB type requires eleven row and eleven column address bits. Also, memory type is important from the aspect of interleaving, since interleaving is only possible between memory banks of the same type.
Hence, from the foregoing, it can be seen that multiple bank memory systems require a complex memory controller. One important .aspect of such a memory controller is to determine which bank is to receive a byte of data. Another important aspect is to determine if interleaving is possible if interleaving is enabled. A still further aspect is to determine the type of memory bank in which the byte of data is to be stored to enable the selection of the proper cycle type. Lastly, it is important to be able to determine if the memory address is a valid address, in other words, if there is an available storage location in one of the memory banks corresponding to the memory address.
One disadvantage in the prior art has been that memory control units generally require the memory bank types and interleaving configuration to be determined at the time the system is configured. This places an extreme restriction on the flexibility of the system and does not permit memory bank interchanges after a system is configured. Also, although interleaving cycle type may be determined, such interleaving may not be possible under a given set of circumstances, such as, for example, when a memory bank to be interleaved is empty or not installed. This can result in a memory control unit losing data by attempting to store it where there are no memory devices.
In addition to the foregoing, multiple bank memory units generally include a pair of memories, an upper memory and a lower memory, within each bank. Each memory may be eight bits wide so that an eight-bit byte may be stored in one of the memories in parallel during a single access cycle or a sixteen-bit word may be stored in parallel during a single cycle with an eight-bit byte being stored in one memory and another eight-bit byte being stored in the other memory. The memories of the memory bank are generally arranged so that a separate row address strobe single is applied to the memories of each individual memory bank while a common upper column address strobe signal is applied to all upper memories and/or a common lower column address strobe signal is applied to all lower memories. A common write-enable signal is also applied to all of the memories. In this manner, a particular memory has been selected by the various combination of row and column address strobe signals.
The above-mentioned prior art memory selection arrangement has exhibited a serious disadvantage in row and column address strobe timing skew. This has resulted because this arrangement causes the row and column address strobes to drive different loads. Such timing skew has been overcome only by utilizing external and relatively high current buffers. Unfortunately, such buffers are expensive to implement and are slow in generating the row and column strobe signals which must be generated at a fast rate, sufficient to permit a central processing unit to execute instructions at a rate to support an entire system, such as a personal computer.